ET-SoC-1 · A physical intuition
Inside the silicon.
A chip is built in layers.
Explore the wires, the switch, and the surface where a channel forms.
01 / ABOVE THE SILICON
A network built in three dimensions
Conductors run sideways. Vias connect the levels. Dielectric keeps the paths apart.
Enable hardware acceleration or try another browser. The labeled sections and controls below still explain each structure.
SECTION / METAL & VIA
schematicTHE STRUCTURE EXPLAINS THE BEHAVIOR
Connected metal, separated signals
A three-dimensional model with selectable components, fixed camera zoom during orbit and stable labels.
Ready.
Generic semiconductor structures, not an ET-SoC-1 physical layout. Materials are color-coded; layer thicknesses and spacing are exaggerated. Motion, charge and gate drive are qualitative, not a calibrated device simulation.
“7 nm” names a process family, not every feature’s width. Four wiring tiers here are a teaching sample, not the chip’s layer count.